10xEngineers Leads the Way in Enhancing RISC-V Compliance Testing
At 10xEngineers, we’re committed to pushing the boundaries of RISC-V technology. We’re excited to share our latest contribution to the RISC-V ecosystem: significant enhancements to the RISC-V ISAC (Instruction Set Architecture Coverage) tool, a critical component of the RISC-V Compatibility Framework (RISCOF).
Stay tuned for more innovations from 10xEngineers – your partner in advancing RISC-V technology.
Bridging the Gap in Privileged Architecture Testing
Our team, led by Muhammad Hammad Bashir and Umer Shahid, in collaboration with industry experts Allen Baum from Esperanto Technologies and Pawan Kumar Sanjaya from the University of Toronto, has addressed a crucial challenge in RISC-V compliance testing.The Challenge:
While RISCOF has been instrumental in ensuring RISC-V processor implementations comply with instruction set simulators like Spike and Sail, it faced limitations in coverage analysis for privileged architecture tests.Our Solution:
We’ve introduced new features in RISC-V ISAC specifically designed to support privileged architecture testing. These enhancements aim to improve compliance testing comprehensively, ensuring that RISC-V implementations adhere to the full spectrum of the ISA, including privileged operations.Key Enhancements to RISC-V ISAC
- New Variables and Functions: We’ve added crucial tracking variables and functions for Privileged Architecture support.
- Virtual Memory Support: Our enhancements cover various virtual memory schemes including SV32, SV39, SV48, and SV59.
- Efficient Coverpoint Writing: We’ve introduced a more concise format for defining coverpoints, utilizing advanced features like ranges, macros, placeholders, and loops.
- Translator Support: This new feature allows for a more intuitive way of writing coverpoints, reducing redundancy and simplifying the process for users.
Impressive Results
- Our enhancements have led to up to a 2x reduction in the size of coverpoints for Physical Memory Protection.
- The new translator support significantly reduces the complexity of writing coverpoints, making the process more efficient and less error-prone.
Impact on the RISC-V Ecosystem
These advancements in RISC-V ISAC are not just technical improvements; they represent a significant step forward for the entire RISC-V community:- Improved Compliance Testing: More comprehensive testing leads to more reliable RISC-V implementations.
- Accelerated Development: Simplified coverpoint writing can speed up the development and verification process.
- Enhanced Quality Assurance: Better coverage analysis ensures higher quality RISC-V processors and implementations.
Dive Deeper into Our Work
We believe in open collaboration and knowledge sharing. To learn more about our enhancements to RISC-V ISAC:Partner with 10xEngineers
As leaders in RISC-V services, including IP development, custom extensions, and verification, we’re uniquely positioned to help you navigate the complexities of RISC-V technology. Whether you’re looking to ensure compliance, optimize performance, or develop custom solutions, our team of experts is here to drive your projects forward. Contact us today to discuss how our cutting-edge research and services can accelerate your RISC-V initiatives.Stay tuned for more innovations from 10xEngineers – your partner in advancing RISC-V technology.