Extend LLVM for RISC-V: Add Your Own Custom Builtin and Instruction

Are you ready to dive deep into the world of compiler development ? Our team has created an exciting new tutorial that demonstrates how to extend LLVM to support a custom RISC-V instruction and corresponding clang builtin. This hands-on guide takes you through the entire process, from adding a new builtin function in Clang to implementing a custom instruction in the RISC-V backend.

CVA6-Platform: Enhancing RISC-V Development with 10x Engineers’ Cloud-V

The Open Hardware Group recently presented the CVA6-Platform at a conference, showcasing an innovative approach to RISC-V software development. We’re proud to announce that this platform leverages Cloud-V, our cloud-based solution developed here at 10x Engineers, to provide developers with flexible and scalable resources for RISC-V projects.

10xEngineers Leads the Way in Enhancing RISC-V Compliance Testing

At 10xEngineers, we’re committed to pushing the boundaries of RISC-V technology. We’re excited to share our latest contribution to the RISC-V ecosystem: significant enhancements to the RISC-V ISAC (Instruction Set Architecture Coverage) tool, a critical component of the RISC-V Compatibility Framework (RISCOF).